From 2fa332ff8d44dec300904538bfa3a196e051dcfd Mon Sep 17 00:00:00 2001 From: Andres Rey Date: Mon, 26 Nov 2018 22:40:10 +0000 Subject: Add all missing metadata bits --- test/test-pages/blogger/expected-metadata.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'test/test-pages/blogger') diff --git a/test/test-pages/blogger/expected-metadata.json b/test/test-pages/blogger/expected-metadata.json index eef4912..1de8a0c 100644 --- a/test/test-pages/blogger/expected-metadata.json +++ b/test/test-pages/blogger/expected-metadata.json @@ -2,5 +2,6 @@ "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices", "Author": null, "Excerpt": "I've written a couple of posts in the past few months but they were all for the blog at work so I figured I'm long overdue for one on Silic...", - "Image": "https:\/\/1.bp.blogspot.com\/-YIPC5jkXkDE\/Vy7YPSqFKWI\/AAAAAAAAAxI\/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB\/w1200-h630-p-nu\/block-diagram.png" + "Image": "https:\/\/1.bp.blogspot.com\/-YIPC5jkXkDE\/Vy7YPSqFKWI\/AAAAAAAAAxI\/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB\/w1200-h630-p-nu\/block-diagram.png", + "Direction": null } \ No newline at end of file -- cgit v1.2.3