From 93ca4484e2720a96f67f6b8edf8d17a39ada2e1b Mon Sep 17 00:00:00 2001 From: Andres Rey Date: Sun, 25 Nov 2018 21:14:25 +0000 Subject: Update test expectations --- test/test-pages/blogger/expected-metadata.json | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'test/test-pages/blogger') diff --git a/test/test-pages/blogger/expected-metadata.json b/test/test-pages/blogger/expected-metadata.json index f912e3b..eef4912 100644 --- a/test/test-pages/blogger/expected-metadata.json +++ b/test/test-pages/blogger/expected-metadata.json @@ -1,5 +1,6 @@ { - "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices", - "Author": null, - "Excerpt": "I've written a couple of posts in the past few months but they were all for the blog at work so I figured I'm long overdue for one on Silic..." -} + "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices", + "Author": null, + "Excerpt": "I've written a couple of posts in the past few months but they were all for the blog at work so I figured I'm long overdue for one on Silic...", + "Image": "https:\/\/1.bp.blogspot.com\/-YIPC5jkXkDE\/Vy7YPSqFKWI\/AAAAAAAAAxI\/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB\/w1200-h630-p-nu\/block-diagram.png" +} \ No newline at end of file -- cgit v1.2.3