From cf1ede0ba8c687d9bfadf1c372546657968f1dd8 Mon Sep 17 00:00:00 2001 From: Andrew Dolgov Date: Fri, 26 Feb 2021 17:35:58 +0300 Subject: pull latest readability-php via composer --- .../test/test-pages/blogger/expected-metadata.json | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 plugins/af_readability/vendor/andreskrey/readability.php/test/test-pages/blogger/expected-metadata.json (limited to 'plugins/af_readability/vendor/andreskrey/readability.php/test/test-pages/blogger/expected-metadata.json') diff --git a/plugins/af_readability/vendor/andreskrey/readability.php/test/test-pages/blogger/expected-metadata.json b/plugins/af_readability/vendor/andreskrey/readability.php/test/test-pages/blogger/expected-metadata.json new file mode 100644 index 000000000..a081c8829 --- /dev/null +++ b/plugins/af_readability/vendor/andreskrey/readability.php/test/test-pages/blogger/expected-metadata.json @@ -0,0 +1,8 @@ +{ + "Author": null, + "Direction": null, + "Excerpt": "I've written a couple of posts in the past few months but they were all for the blog at work so I figured I'm long overdue for one on Silic...", + "Image": "https:\/\/1.bp.blogspot.com\/-YIPC5jkXkDE\/Vy7YPSqFKWI\/AAAAAAAAAxI\/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB\/w1200-h630-p-nu\/block-diagram.png", + "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices", + "SiteName": null +} -- cgit v1.2.3