diff options
| author | Andres Rey <[email protected]> | 2017-07-09 11:32:02 +0100 |
|---|---|---|
| committer | Andres Rey <[email protected]> | 2017-07-09 11:32:02 +0100 |
| commit | 8626e09f7bb3f282f47802326c53a05edf820f8a (patch) | |
| tree | adb18c6a22a7a4c1ba3f8bb9e8d2582bda26addd | |
| parent | 451cd8d7705c7f5fbf655764382320ddf2a29ea3 (diff) | |
Initial correction of new test cases
| -rw-r--r-- | .gitignore | 1 | ||||
| -rw-r--r-- | README.md | 12 | ||||
| -rw-r--r-- | test/test-pages/blogger/expected.html | 184 | ||||
| -rw-r--r-- | test/test-pages/clean-links/expected.html | 2 | ||||
| -rw-r--r-- | test/test-pages/cnet/expected.html | 68 | ||||
| -rw-r--r-- | test/test-pages/gmw/expected.html | 111 | ||||
| -rw-r--r-- | test/test-pages/msn/expected.html | 39 |
7 files changed, 184 insertions, 233 deletions
@@ -1,4 +1,3 @@ -~* .idea/ vendor composer.lock @@ -88,11 +88,17 @@ Readability uses the Element interface and class from *The PHP League's* **[html ## To-do -100% of the original readability code was ported, at least until the last commit when I started this project ([13 Aug 2016](https://github.com/mozilla/readability/commit/71aa562387fa507b0bac30ae7144e1df7ba8a356)). There are a lot of `TODO`s around the code, which are the part that need to be finished. - - Right now the Readability object is an extension of the Element object of html-to-markdown. This is a problem because you lose context. The scoring when creating a new Readability object must be reloaded manually. The DOMDocument object is consistent across the same document. You change one value here and that will update all other nodes in other variables. By using the element interface you lose that reference and the score must be restored manually. Ideally, the Readability object should be an extension of the DOMDocument or DOMElement objects, the score should be saved within that object and no restoration or recalculation would be needed. - There are a lot of problems with responsabilities. Right now there are two classes: HTMLParser and Readability. HTMLParser does a lot of things that should be a responsibility of Readability. It also does a lot of things that should be part of another class, specially when building the final article DOMDocument. ## How it works -Readability parses all the text with DOMDocument, scans the text nodes and gives the a score, based on the amount of words, links and type of element. Then it selects the highest scoring element and creates a new DOMDocument with all its siblings. Each sibling is scored to discard useless elements, like nav bars, empty nodes, etc.
\ No newline at end of file +Readability parses all the text with DOMDocument, scans the text nodes and gives the a score, based on the amount of words, links and type of element. Then it selects the highest scoring element and creates a new DOMDocument with all its siblings. Each sibling is scored to discard useless elements, like nav bars, empty nodes, etc. + +## Code porting + +Current version follows the latest version of readability.js as of [05 May 2015](https://github.com/mozilla/readability/commit/f0edc77cb58ef52890e3065cf2b0e334d940feb2). + +### TO-DOs of the current port: + + - Port `_cleanStyles` to avoid style attributes inside other tags (like `<p style="hello ">`)
\ No newline at end of file diff --git a/test/test-pages/blogger/expected.html b/test/test-pages/blogger/expected.html index 7b55749..6dfed38 100644 --- a/test/test-pages/blogger/expected.html +++ b/test/test-pages/blogger/expected.html @@ -1,127 +1,57 @@ -<div id="readability-page-1" class="page"> - <div class="post-body entry-content" id="post-body-932306423056216142" itemprop="description articleBody"> - <p style="display: inline;" class="readability-styled"> I've written a couple of posts in the past few months but they were all for </p><a href="http://blog.ioactive.com/search/label/Andrew%20Zonenberg">the blog at work</a> - <p style="display: inline;" class="readability-styled"> so I figured I'm long overdue for one on Silicon Exposed.</p> - <p> - <h2> So what's a GreenPak?</h2> - </p> - <p style="display: inline;" class="readability-styled"> Silego Technology is a fabless semiconductor company located in the SF Bay area, which makes (among other things) a line of programmable logic devices known as GreenPak. Their </p><a href="http://www.silego.com/products/greenpak5.html">5th generation parts</a> - <p style="display: inline;" class="readability-styled"> were just announced, but I started this project before that happened so I'm still targeting the </p><a href="http://www.silego.com/products/greenpak4.html">4th generation</a> - <p style="display: inline;" class="readability-styled">.</p> - <p> GreenPak devices are kind of like itty bitty <a href="http://www.cypress.com/products/32-bit-arm-cortex-m-psoc">PSoCs</a> - they have a mixed signal fabric with an ADC, DACs, comparators, voltage references, plus a digital LUT/FF fabric and some typical digital MCU peripherals like counters and oscillators (but no CPU).</p> - <p> It's actually an interesting architecture - FPGAs (including some devices marketed as CPLDs) are a 2D array of LUTs connected via wires to adjacent cells, and true (product term) CPLDs are a star topology of AND-OR arrays connected by a crossbar. GreenPak, on the other hand, is a star topology of LUTs, flipflops, and analog/digital hard IP connected to a crossbar.</p> - <p> Without further ado, here's a block diagram showing all the cool stuff you get in the SLG46620V:</p> - <p> - <table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container"> - <tbody> - <tr> - <td> - <a href="https://1.bp.blogspot.com/-YIPC5jkXkDE/Vy7YPSqFKWI/AAAAAAAAAxI/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB/s1600/block-diagram.png" imageanchor="1"><img border="0" height="512" src="https://1.bp.blogspot.com/-YIPC5jkXkDE/Vy7YPSqFKWI/AAAAAAAAAxI/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB/s640/block-diagram.png" width="640" /></a> - </td> - </tr> - <tr> - <td class="tr-caption">SLG46620V block diagram (from device datasheet)</td> - </tr> - </tbody> - </table> They're also tiny (the SLG46620V is a 20-pin 0.4mm pitch STQFN measuring 2x3 mm, and the lower gate count SLG46140V is a mere 1.6x2 mm) and probably the cheapest programmable logic device on the market - $0.50 in low volume and less than $0.40 in larger quantities.</p> - <p> The Vdd range of GreenPak4 is huge, more like what you'd expect from an MCU than an FPGA! It can run on anything from 1.8 to 5V, although performance is only specified at 1.8, 3.3, and 5V nominal voltages. There's also a dual-rail version that trades one of the GPIO pins for a second power supply pin, allowing you to interface to logic at two different voltage levels.</p> - <p> To support low-cost/space-constrained applications, they even have the configuration memory on die. It's one-time programmable and needs external Vpp to program (presumably Silego didn't want to waste die area on charge pumps that would only be used once) but has a SRAM programming mode for prototyping.</p> - <p> The best part is that the development software (GreenPak Designer) is free of charge and provided for all major operating systems including Linux! Unfortunately, the only supported design entry method is schematic entry and there's no way to write your design in a HDL.</p> - <p> While schematics may be fine for quick tinkering on really simple designs, they quickly get unwieldy. The nightmare of a circuit shown below is just a bunch of counters hooked up to LEDs that blink at various rates.</p> - <p> - <table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container"> - <tbody> - <tr> - <td> - <a href="https://1.bp.blogspot.com/-k3naUT3uXao/Vy7WFac246I/AAAAAAAAAw8/mePy_ostO8QJra5ZJrbP2WGhTlJ0B_r8gCLcB/s1600/schematic-from-hell.png" imageanchor="1"><img border="0" height="334" src="https://1.bp.blogspot.com/-k3naUT3uXao/Vy7WFac246I/AAAAAAAAAw8/mePy_ostO8QJra5ZJrbP2WGhTlJ0B_r8gCLcB/s640/schematic-from-hell.png" width="640" /></a> - </td> - </tr> - <tr> - <td class="tr-caption">Schematic from hell!</td> - </tr> - </tbody> - </table> As if this wasn't enough of a problem, the largest GreenPak4 device (the SLG46620V) is split into two halves with limited routing between them, and the GUI doesn't help the user manage this complexity at all - you have to draw your schematic in two halves and add "cross connections" between them.</p> - <p> The icing on the cake is that schematics are a pain to diff and collaborate on. Although GreenPak schematics are XML based, which is a touch better than binary, who wants to read a giant XML diff and try to figure out what's going on in the circuit?</p> - <p> This isn't going to be a post on the quirks of Silego's software, though - that would be boring. As it turns out, there's one more exciting feature of these chips that I didn't mention earlier: the configuration bitstream is 100% documented in the device datasheet! This is unheard of in the programmable logic world. As Nick of Arachnid Labs <a href="http://www.arachnidlabs.com/blog/2015/03/30/greenpak/">says</a>, the chip is "just dying for someone to write a VHDL or Verilog compiler for it". As you can probably guess by from the title of this post, I've been busy doing exactly that.</p> - <p> - <h2> Great! How does it work?</h2> - </p> - <p style="display: inline;" class="readability-styled"> Rather than wasting time writing a synthesizer, I decided to write a GreenPak technology library for Clifford Wolf's excellent open source synthesis tool, </p><a href="http://www.clifford.at/yosys/">Yosys</a> - <p style="display: inline;" class="readability-styled">, and then make a place-and-route tool to turn that into a final netlist. The post-PAR netlist can then be loaded into GreenPak Designer in order to program the device.</p> - <p> The first step of the process is to run the "synth_greenpak4" Yosys flow on the Verilog source. This runs a generic RTL synthesis pass, then some coarse-grained extraction passes to infer shift register and counter cells from behavioral logic, and finally maps the remaining logic to LUT/FF cells and outputs a JSON-formatted netlist.</p> - <p> Once the design has been synthesized, my tool (named, surprisingly, gp4par) is then launched on the netlist. It begins by parsing the JSON and constructing a directed graph of cell objects in memory. A second graph, containing all of the primitives in the device and the legal connections between them, is then created based on the device specified on the command line. (As of now only the SLG46620V is supported; the SLG46621V can be added fairly easily but the SLG46140V has a slightly different microarchitecture which will require a bit more work to support.)</p> - <p> After the graphs are generated, each node in the netlist graph is assigned a numeric label identifying the type of cell and each node in the device graph is assigned a list of legal labels: for example, an I/O buffer site is legal for an input buffer, output buffer, or bidirectional buffer.</p> - <p> - <table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container"> - <tbody> - <tr> - <td> - <a href="https://2.bp.blogspot.com/-kIekczO693g/Vy7dBqYifXI/AAAAAAAAAxc/hMNJBs5bedIQOrBzzkhq4gbmhR-n58EQwCLcB/s1600/graph-labels.png" imageanchor="1"><img border="0" height="141" src="https://2.bp.blogspot.com/-kIekczO693g/Vy7dBqYifXI/AAAAAAAAAxc/hMNJBs5bedIQOrBzzkhq4gbmhR-n58EQwCLcB/s400/graph-labels.png" width="400" /></a> - </td> - </tr> - <tr> - <td class="tr-caption">Example labeling for a subset of the netlist and device graphs</td> - </tr> - </tbody> - </table> The labeled nodes now need to be placed. The initial placement uses a simple greedy algorithm to create a valid (although not necessarily optimal or even routable) placement:</p><br/> - <ol> - <li>Loop over the cells in the netlist. If any cell has a LOC constraint, which locks the cell to a specific physical site, attempt to assign the node to the specified site. If the specified node is the wrong type, doesn't exist, or is already used by another constrained node, the constraint is invalid so fail with an error.</li> - <li>Loop over all of the unconstrained cells in the netlist and assign them to the first unused site with the right label. If none are available, the design is too big for the device so fail with an error.</li> - </ol> - <p style="display: inline;" class="readability-styled"> Once the design is placed, the placement optimizer then loops over the design and attempts to improve it. A simulated annealing algorithm is used, where changes to the design are accepted unconditionally if they make the placement better, and with a random, gradually decreasing probability if they make it worse. The optimizer terminates when the design receives a perfect score (indicating an optimal placement) or if it stops making progress for several iterations. Each iteration does the following:</p><br/> - <ol> - <li>Compute a score for the current design based on the number of unroutable nets, the amount of routing congestion (number of nets crossing between halves of the device), and static timing analysis (not yet implemented, always zero).</li> - <li>Make a list of nodes that contributed to this score in some way (having some attached nets unroutable, crossing to the other half of the device, or failing timing).</li> - <li>Remove nodes from the list that are LOC'd to a specific location since we're not allowed to move them.</li> - <li>Remove nodes from the list that have only one legal placement in the device (for example, oscillator hard IP) since there's nowhere else for them to go.</li> - <li>Pick a node from the remainder of the list at random. Call this our pivot.</li> - <li>Find a list of candidate placements for the pivot: </li> - <ol> - <li>Consider all routable placements in the other half of the device.</li> - <li>If none were found, consider all routable placements anywhere in the device.</li> - <li>If none were found, consider all placements anywhere in the device even if they're not routable.</li> - </ol> - <li>Pick one of the candidates at random and move the pivot to that location. If another cell in the netlist is already there, put it in the vacant site left by the pivot.</li> - <li>Re-compute the score for the design. If it's better, accept this change and start the next iteration.</li> - <li>If the score is worse, accept it with a random probability which decreases as the iteration number goes up. If the change is not accepted, restore the previous placement.</li> - </ol> - <p style="display: inline;" class="readability-styled"> After optimization, the design is checked for routability. If any edges in the netlist graph don't correspond to edges in the device graph, the user probably asked for something impossible (for example, trying to hook a flipflop's output to a comparator's reference voltage input) so fail with an error.</p> - <p> The design is then routed. This is quite simple due to the crossbar structure of the device. For each edge in the netlist:</p><br/> - <ol> - <li>If dedicated (non-fabric) routing is used for this path, configure the destination's input mux appropriately and stop.</li> - <li>If the source and destination are in the same half of the device, configure the destination's input mux appropriately and stop.</li> - <li>A cross-connection must be used. Check if we already used one to bring the source signal to the other half of the device. If found, configure the destination to route from that cross-connection and stop.</li> - <li>Check if we have any cross-connections left going in this direction. If they're all used, the design is unroutable due to congestion so fail with an error.</li> - <li>Pick the next unused cross-connection and configure it to route from the source. Configure the destination to route from the cross-connection and stop.</li> - </ol> - <p style="display: inline;" class="readability-styled"> Once routing is finished, run a series of post-PAR design rule checks. These currently include the following:</p><br/> - <ul> - <li>If any node has no loads, generate a warning</li> - <li>If an I/O buffer is connected to analog hard IP, fail with an error if it's not configured in analog mode.</li> - <li>Some signals (such as comparator inputs and oscillator power-down controls) are generated by a shared mux and fed to many loads. If different loads require conflicting settings for the shared mux, fail with an error.</li> - </ul> - <p style="display: inline;" class="readability-styled"> If DRC passes with no errors, configure all of the individual cells in the netlist based on the HDL parameters. Fail with an error if an invalid configuration was requested.</p> - <p> Finally, generate the bitstream from all of the per-cell configuration and write it to a file.</p> - <p> - <h2> Great, let's get started!</h2> If you don't already have one, you'll need to buy a <a href="http://www.silego.com/buy/index.php?main_page=product_info&products_id=388">GreenPak4 development kit</a>. The kit includes samples of the SLG46620V (among other devices) and a programmer/emulation board. While you're waiting for it to arrive, install <a href="http://www.silego.com/softdoc/software.html">GreenPak Designer</a>.</p> - <p> Download and install Yosys. Although Clifford is pretty good at merging my pull requests, only <a href="https://github.com/azonenberg/yosys/">my fork on Github</a> is guaranteed to have the most up-to-date support for GreenPak devices so don't be surprised if you can't use a bleeding-edge feature with mainline Yosys.</p> - <p> Download and install gp4par. You can get it from <a href="https://github.com/azonenberg/openfpga/">the Github repository</a>.</p> - <p> Write your HDL, compile with Yosys, P&R with gp4par, and import the bitstream into GreenPak Designer to program the target device. The most current gp4par manual is included in LaTeX source form in the source tree and is automatically built as part of the compile process. If you're just browsing, there's a <a href="http://thanatos.virtual.antikernel.net/unlisted/gp4-hdl.pdf">relatively recent PDF version</a> on my web server.</p> - <p> If you'd like to see the Verilog that produced the nightmare of a schematic I showed above, <a href="https://github.com/azonenberg/openfpga/blob/master/tests/greenpak4/Blinky/Blinky.v">here it is</a>.</p> - <p> Be advised that this project is still very much a work in progress and there are still a number of SLG46620V features I don't support (see the manual for exact details).</p> - <p> - <h2> I love it / it segfaulted / there's a problem in the manual!</h2> Hop in our IRC channel (##openfpga on Freenode) and let me know. Feedback is great, pull requests are even better,</p> - <p> - <h2> You're competing with Silego's IDE. Have they found out and sued you yet?</h2> Nope. They're fully aware of what I'm doing and are rolling out the red carpet for me. They love the idea of a HDL flow as an alternative to schematic entry and are pretty amazed at how fast it's coming together.</p> - <p> After I reported a few bugs in their datasheets they decided to skip the middleman and give me direct access to the engineer who writes their documentation so that I can get faster responses. The last time I found a problem (two different parts of the datasheet contradicted each other) an updated datasheet was in my inbox and on their website by the next day. I only wish Xilinx gave me that kind of treatment!</p> - <p> They've even <a href="https://twitter.com/SilegoTech/status/717018987771469824">offered me free hardware</a> to help me add support for their latest product family, although I plan to get GreenPak4 support to a more stable state before taking them up on the offer.</p> - <p> - <h2> So what's next?</h2> - </p> - <p style="display: inline;" class="readability-styled"> Better testing, for starters. I have to verify functionality by hand with a DMM and oscilloscope, which is time consuming.</p> - <p> My contact at Silego says they're going to be giving me documentation on the SRAM emulation interface soon, so I'm going to make a hardware-in-loop test platform that connects to my desktop and the Silego ZIF socket, and lets me load new bitstreams via a scriptable interface. It'll have FPGA-based digital I/O as well as an ADC and DAC on every device pin, plus an adjustable voltage regulator for power, so I can feed in arbitrary mixed-signal test waveforms and write PC-based unit tests to verify correct behavior.</p> - <p> Other than that, I want to finish support for the SLG46620V in the next month or two. The SLG46621V will be an easy addition since only one pin and the relevant configuration bits have changed from the 46620 (I suspect they're the same die, just bonded out differently).</p> - <p> Once that's done I'll have to do some more extensive work to add the SLG46140V since the architecture is a bit different (a lot of the combinatorial logic is merged into multi-function blocks). Luckily, the 46140 has a lot in common architecturally with the GreenPak5 family, so once that's done GreenPak5 will probably be a lot easier to add support for.</p> - <p> My thanks go out to Clifford Wolf, whitequark, the IRC users in ##openfpga, and everyone at Silego I've worked with to help make this possible. I hope that one day this project will become mature enough that Silego will ship it as an officially supported extension to GreenPak Designer, making history by becoming the first modern programmable logic vendor to ship a fully open source synthesis and P&R suite. </p> - </div> -</div>
\ No newline at end of file +<div class="post-body entry-content" id="post-body-932306423056216142" itemprop="description articleBody"><p> + I've written a couple of posts in the past few months but they were all for </p><a href="http://blog.ioactive.com/search/label/Andrew%20Zonenberg">the blog at work</a><p> so I figured I'm long overdue for one on Silicon Exposed.</p><p><h2> + So what's a GreenPak?</h2> + </p><p> Silego Technology is a fabless semiconductor company located in the SF Bay area, which makes (among other things) a line of programmable logic devices known as GreenPak. Their </p><a href="http://www.silego.com/products/greenpak5.html">5th generation parts</a><p> were just announced, but I started this project before that happened so I'm still targeting the </p><a href="http://www.silego.com/products/greenpak4.html">4th generation</a><p>.</p><p> GreenPak devices are kind of like itty bitty <a href="http://www.cypress.com/products/32-bit-arm-cortex-m-psoc">PSoCs</a> - they have a mixed signal fabric with an ADC, DACs, comparators, voltage references, plus a digital LUT/FF fabric and some typical digital MCU peripherals like counters and oscillators (but no CPU).<p> It's actually an interesting architecture - FPGAs (including some devices marketed as CPLDs) are a 2D array of LUTs connected via wires to adjacent cells, and true (product term) CPLDs are a star topology of AND-OR arrays connected by a crossbar. GreenPak, on the other hand, is a star topology of LUTs, flipflops, and analog/digital hard IP connected to a crossbar.<p> Without further ado, here's a block diagram showing all the cool stuff you get in the SLG46620V:<p><table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody><tr><td style="text-align: center;"> + <a href="https://1.bp.blogspot.com/-YIPC5jkXkDE/Vy7YPSqFKWI/AAAAAAAAAxI/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB/s1600/block-diagram.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="512" src="https://1.bp.blogspot.com/-YIPC5jkXkDE/Vy7YPSqFKWI/AAAAAAAAAxI/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB/s640/block-diagram.png" width="640"></img></a> + </td> + </tr><tr><td class="tr-caption" style="text-align: center;">SLG46620V block diagram (from device datasheet)</td> + </tr></tbody></table> + They're also tiny (the SLG46620V is a 20-pin 0.4mm pitch STQFN measuring 2x3 mm, and the lower gate count SLG46140V is a mere 1.6x2 mm) and probably the cheapest programmable logic device on the market - $0.50 in low volume and less than $0.40 in larger quantities.<p> The Vdd range of GreenPak4 is huge, more like what you'd expect from an MCU than an FPGA! It can run on anything from 1.8 to 5V, although performance is only specified at 1.8, 3.3, and 5V nominal voltages. There's also a dual-rail version that trades one of the GPIO pins for a second power supply pin, allowing you to interface to logic at two different voltage levels.<p> To support low-cost/space-constrained applications, they even have the configuration memory on die. It's one-time programmable and needs external Vpp to program (presumably Silego didn't want to waste die area on charge pumps that would only be used once) but has a SRAM programming mode for prototyping.<p> The best part is that the development software (GreenPak Designer) is free of charge and provided for all major operating systems including Linux! Unfortunately, the only supported design entry method is schematic entry and there's no way to write your design in a HDL.<p> While schematics may be fine for quick tinkering on really simple designs, they quickly get unwieldy. The nightmare of a circuit shown below is just a bunch of counters hooked up to LEDs that blink at various rates.<p><table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody><tr><td style="text-align: center;"> + <a href="https://1.bp.blogspot.com/-k3naUT3uXao/Vy7WFac246I/AAAAAAAAAw8/mePy_ostO8QJra5ZJrbP2WGhTlJ0B_r8gCLcB/s1600/schematic-from-hell.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="334" src="https://1.bp.blogspot.com/-k3naUT3uXao/Vy7WFac246I/AAAAAAAAAw8/mePy_ostO8QJra5ZJrbP2WGhTlJ0B_r8gCLcB/s640/schematic-from-hell.png" width="640"></img></a> + </td> + </tr><tr><td class="tr-caption" style="text-align: center;">Schematic from hell!</td> + </tr></tbody></table> + As if this wasn't enough of a problem, the largest GreenPak4 device (the SLG46620V) is split into two halves with limited routing between them, and the GUI doesn't help the user manage this complexity at all - you have to draw your schematic in two halves and add "cross connections" between them.<p> The icing on the cake is that schematics are a pain to diff and collaborate on. Although GreenPak schematics are XML based, which is a touch better than binary, who wants to read a giant XML diff and try to figure out what's going on in the circuit?<p> This isn't going to be a post on the quirks of Silego's software, though - that would be boring. As it turns out, there's one more exciting feature of these chips that I didn't mention earlier: the configuration bitstream is 100% documented in the device datasheet! This is unheard of in the programmable logic world. As Nick of Arachnid Labs <a href="http://www.arachnidlabs.com/blog/2015/03/30/greenpak/">says</a>, the chip is "just dying for someone to write a VHDL or Verilog compiler for it". As you can probably guess by from the title of this post, I've been busy doing exactly that.<p><h2> + Great! How does it work?</h2> + </p></p></p></p></p></p></p></p></p></p></p></p><p> Rather than wasting time writing a synthesizer, I decided to write a GreenPak technology library for Clifford Wolf's excellent open source synthesis tool, </p><a href="http://www.clifford.at/yosys/">Yosys</a><p>, and then make a place-and-route tool to turn that into a final netlist. The post-PAR netlist can then be loaded into GreenPak Designer in order to program the device.</p><p> The first step of the process is to run the "synth_greenpak4" Yosys flow on the Verilog source. This runs a generic RTL synthesis pass, then some coarse-grained extraction passes to infer shift register and counter cells from behavioral logic, and finally maps the remaining logic to LUT/FF cells and outputs a JSON-formatted netlist.<p> Once the design has been synthesized, my tool (named, surprisingly, gp4par) is then launched on the netlist. It begins by parsing the JSON and constructing a directed graph of cell objects in memory. A second graph, containing all of the primitives in the device and the legal connections between them, is then created based on the device specified on the command line. (As of now only the SLG46620V is supported; the SLG46621V can be added fairly easily but the SLG46140V has a slightly different microarchitecture which will require a bit more work to support.)<p> After the graphs are generated, each node in the netlist graph is assigned a numeric label identifying the type of cell and each node in the device graph is assigned a list of legal labels: for example, an I/O buffer site is legal for an input buffer, output buffer, or bidirectional buffer.<p><table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody><tr><td style="text-align: center;"> + <a href="https://2.bp.blogspot.com/-kIekczO693g/Vy7dBqYifXI/AAAAAAAAAxc/hMNJBs5bedIQOrBzzkhq4gbmhR-n58EQwCLcB/s1600/graph-labels.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="141" src="https://2.bp.blogspot.com/-kIekczO693g/Vy7dBqYifXI/AAAAAAAAAxc/hMNJBs5bedIQOrBzzkhq4gbmhR-n58EQwCLcB/s400/graph-labels.png" width="400"></img></a> + </td> + </tr><tr><td class="tr-caption" style="text-align: center;">Example labeling for a subset of the netlist and device graphs</td> + </tr></tbody></table> + The labeled nodes now need to be placed. The initial placement uses a simple greedy algorithm to create a valid (although not necessarily optimal or even routable) placement:</p></p></p></p><br></br><ol><li>Loop over the cells in the netlist. If any cell has a LOC constraint, which locks the cell to a specific physical site, attempt to assign the node to the specified site. If the specified node is the wrong type, doesn't exist, or is already used by another constrained node, the constraint is invalid so fail with an error.</li> + <li>Loop over all of the unconstrained cells in the netlist and assign them to the first unused site with the right label. If none are available, the design is too big for the device so fail with an error.</li> + </ol><p> + Once the design is placed, the placement optimizer then loops over the design and attempts to improve it. A simulated annealing algorithm is used, where changes to the design are accepted unconditionally if they make the placement better, and with a random, gradually decreasing probability if they make it worse. The optimizer terminates when the design receives a perfect score (indicating an optimal placement) or if it stops making progress for several iterations. Each iteration does the following:</p><br></br><ol><li>Compute a score for the current design based on the number of unroutable nets, the amount of routing congestion (number of nets crossing between halves of the device), and static timing analysis (not yet implemented, always zero).</li> + <li>Make a list of nodes that contributed to this score in some way (having some attached nets unroutable, crossing to the other half of the device, or failing timing).</li> + <li>Remove nodes from the list that are LOC'd to a specific location since we're not allowed to move them.</li> + <li>Remove nodes from the list that have only one legal placement in the device (for example, oscillator hard IP) since there's nowhere else for them to go.</li> + <li>Pick a node from the remainder of the list at random. Call this our pivot.</li> + <li>Find a list of candidate placements for the pivot: </li> + <ol><li>Consider all routable placements in the other half of the device.</li> + <li>If none were found, consider all routable placements anywhere in the device.</li> + <li>If none were found, consider all placements anywhere in the device even if they're not routable.</li> + </ol><li>Pick one of the candidates at random and move the pivot to that location. If another cell in the netlist is already there, put it in the vacant site left by the pivot.</li> + <li>Re-compute the score for the design. If it's better, accept this change and start the next iteration.</li> + <li>If the score is worse, accept it with a random probability which decreases as the iteration number goes up. If the change is not accepted, restore the previous placement.</li> + </ol><p> + After optimization, the design is checked for routability. If any edges in the netlist graph don't correspond to edges in the device graph, the user probably asked for something impossible (for example, trying to hook a flipflop's output to a comparator's reference voltage input) so fail with an error.</p><p> The design is then routed. This is quite simple due to the crossbar structure of the device. For each edge in the netlist:</p><br></br><ol><li>If dedicated (non-fabric) routing is used for this path, configure the destination's input mux appropriately and stop.</li> + <li>If the source and destination are in the same half of the device, configure the destination's input mux appropriately and stop.</li> + <li>A cross-connection must be used. Check if we already used one to bring the source signal to the other half of the device. If found, configure the destination to route from that cross-connection and stop.</li> + <li>Check if we have any cross-connections left going in this direction. If they're all used, the design is unroutable due to congestion so fail with an error.</li> + <li>Pick the next unused cross-connection and configure it to route from the source. Configure the destination to route from the cross-connection and stop.</li> + </ol><p> + Once routing is finished, run a series of post-PAR design rule checks. These currently include the following:</p><br></br><ul><li>If any node has no loads, generate a warning</li> + <li>If an I/O buffer is connected to analog hard IP, fail with an error if it's not configured in analog mode.</li> + <li>Some signals (such as comparator inputs and oscillator power-down controls) are generated by a shared mux and fed to many loads. If different loads require conflicting settings for the shared mux, fail with an error.</li> + </ul><p> + If DRC passes with no errors, configure all of the individual cells in the netlist based on the HDL parameters. Fail with an error if an invalid configuration was requested.</p><p> Finally, generate the bitstream from all of the per-cell configuration and write it to a file.<p><h2> + Great, let's get started!</h2> + If you don't already have one, you'll need to buy a <a href="http://www.silego.com/buy/index.php?main_page=product_info&products_id=388">GreenPak4 development kit</a>. The kit includes samples of the SLG46620V (among other devices) and a programmer/emulation board. While you're waiting for it to arrive, install <a href="http://www.silego.com/softdoc/software.html">GreenPak Designer</a>.<p> Download and install Yosys. Although Clifford is pretty good at merging my pull requests, only <a href="https://github.com/azonenberg/yosys/">my fork on Github</a> is guaranteed to have the most up-to-date support for GreenPak devices so don't be surprised if you can't use a bleeding-edge feature with mainline Yosys.<p> Download and install gp4par. You can get it from <a href="https://github.com/azonenberg/openfpga/">the Github repository</a>.<p> Write your HDL, compile with Yosys, P&R with gp4par, and import the bitstream into GreenPak Designer to program the target device. The most current gp4par manual is included in LaTeX source form in the source tree and is automatically built as part of the compile process. If you're just browsing, there's a <a href="http://thanatos.virtual.antikernel.net/unlisted/gp4-hdl.pdf">relatively recent PDF version</a> on my web server.<p> If you'd like to see the Verilog that produced the nightmare of a schematic I showed above, <a href="https://github.com/azonenberg/openfpga/blob/master/tests/greenpak4/Blinky/Blinky.v">here it is</a>.<p> Be advised that this project is still very much a work in progress and there are still a number of SLG46620V features I don't support (see the manual for exact details).<p><h2> + I love it / it segfaulted / there's a problem in the manual!</h2> + Hop in our IRC channel (##openfpga on Freenode) and let me know. Feedback is great, pull requests are even better,<p><h2> + You're competing with Silego's IDE. Have they found out and sued you yet?</h2> + Nope. They're fully aware of what I'm doing and are rolling out the red carpet for me. They love the idea of a HDL flow as an alternative to schematic entry and are pretty amazed at how fast it's coming together.<p> After I reported a few bugs in their datasheets they decided to skip the middleman and give me direct access to the engineer who writes their documentation so that I can get faster responses. The last time I found a problem (two different parts of the datasheet contradicted each other) an updated datasheet was in my inbox and on their website by the next day. I only wish Xilinx gave me that kind of treatment!<p> They've even <a href="https://twitter.com/SilegoTech/status/717018987771469824">offered me free hardware</a> to help me add support for their latest product family, although I plan to get GreenPak4 support to a more stable state before taking them up on the offer.<p><h2> + So what's next?</h2> + </p></p></p></p></p></p></p></p></p></p></p></p><p> Better testing, for starters. I have to verify functionality by hand with a DMM and oscilloscope, which is time consuming.</p><p> My contact at Silego says they're going to be giving me documentation on the SRAM emulation interface soon, so I'm going to make a hardware-in-loop test platform that connects to my desktop and the Silego ZIF socket, and lets me load new bitstreams via a scriptable interface. It'll have FPGA-based digital I/O as well as an ADC and DAC on every device pin, plus an adjustable voltage regulator for power, so I can feed in arbitrary mixed-signal test waveforms and write PC-based unit tests to verify correct behavior.<p> Other than that, I want to finish support for the SLG46620V in the next month or two. The SLG46621V will be an easy addition since only one pin and the relevant configuration bits have changed from the 46620 (I suspect they're the same die, just bonded out differently).<p> Once that's done I'll have to do some more extensive work to add the SLG46140V since the architecture is a bit different (a lot of the combinatorial logic is merged into multi-function blocks). Luckily, the 46140 has a lot in common architecturally with the GreenPak5 family, so once that's done GreenPak5 will probably be a lot easier to add support for.<p> My thanks go out to Clifford Wolf, whitequark, the IRC users in ##openfpga, and everyone at Silego I've worked with to help make this possible. I hope that one day this project will become mature enough that Silego will ship it as an officially supported extension to GreenPak Designer, making history by becoming the first modern programmable logic vendor to ship a fully open source synthesis and P&R suite. + + </p></p></p></p></div>
\ No newline at end of file diff --git a/test/test-pages/clean-links/expected.html b/test/test-pages/clean-links/expected.html index b8cf601..a836d91 100644 --- a/test/test-pages/clean-links/expected.html +++ b/test/test-pages/clean-links/expected.html @@ -1,4 +1,4 @@ -<div><td> +<div><td> <h3 align="center ">Study Webtext</h3> <h2 align="center "><span color="Maroon
 " face="Lucida Handwriting ">"Bartleby the Scrivener: A Story of Wall-Street " </span>(1853) <br></br> Herman Melville</h2> diff --git a/test/test-pages/cnet/expected.html b/test/test-pages/cnet/expected.html index 31d2af5..1f5675a 100644 --- a/test/test-pages/cnet/expected.html +++ b/test/test-pages/cnet/expected.html @@ -1,25 +1,43 @@ -<div id="readability-page-1" class="page"> - <div class="col-7 article-main-body row" itemprop="articleBody" data-component="lazyloadImages"> - <figure class="image image-medium - pull-right" section="shortcodeImage"><span class="imageContainer"><span itemprop="image" itemscope="" itemtype="https://schema.org/ImageObject"><img src="https://cnet1.cbsistatic.com/img/nAMdBzIE1ogVw5bOBZBaiJCt3Ro=/570x0/2014/03/21/863df5d9-e8b8-4b38-851b-5e3f77f2cf0e/mark-zuckerberg-facebook-home-10671610x407.jpg" class="" alt="" width="570" height="0"/><meta itemprop="url" content="https://cnet1.cbsistatic.com/img/nAMdBzIE1ogVw5bOBZBaiJCt3Ro=/570x0/2014/03/21/863df5d9-e8b8-4b38-851b-5e3f77f2cf0e/mark-zuckerberg-facebook-home-10671610x407.jpg"/><meta itemprop="height" content="0"/><meta itemprop="width" content="570"/></span></span> - <figcaption><span class="caption"><p>Facebook CEO Mark Zuckerberg, the man with the acquisition plan.</p></span><span class="credit">Photo by James Martin/CNET - </span></figcaption> - </figure> - <p>Anyone who has ever been involved in closing a billion-dollar acquisition deal will tell you that you don't go in without a clear, well thought out plan.</p> - <p>Facebook CEO Mark Zuckerberg knows a thing or two about how to seal the deal on blockbuster buys. After all, he's the man behind his company's <a href="https://www.cnet.com/news/facebook-closes-19-billion-deal-for-whatsapp/" target="_blank">$19 billion acquisition</a> of WhatsApp, he <a href="https://www.cnet.com/news/zuckerberg-did-1-billion-instagram-deal-on-his-own/" target="_blank">personally brokered</a> its $1 billion buyout of <a href="https://www.cnet.com/news/why-facebook-plunked-down-1-billion-to-buy-instagram/" target="_blank">Instagram</a> and closed the <a href="https://www.cnet.com/news/facebook-to-buy-oculus-for-2-billion/" target="_blank">$3 billion deal</a> to buy Oculus VR.</p> - <p>Zuckerberg offered a primer on the strategies he and his company employ when they see an attractive target during testimony Tuesday <a href="https://www.cnet.com/news/zenimax-sues-oculus-over-virtual-reality-rift-tech/">in a lawsuit with ZeniMax Media</a>, which accuses Oculus and Facebook of "misappropriating" trade secrets and copyright infringement. At the heart of the lawsuit is technology that helped create liftoff for virtual reality, one of the <a href="http://www.cbsnews.com/videos/the-reality-of-the-virtual-world/" target="_blank" data-component="externalLink">hottest gadget trends today.</a></p> - <p>A key Facebook approach is building a long-term relationship with your target, Zuckerberg said at the trial. These deals don't just pop up over night, he said according to a transcript reviewed by <a href="http://www.businessinsider.com/mark-zuckerberg-explains-facebooks-acquisition-strategy-2017-1" target="_blank" data-component="externalLink">Business Insider</a>. They take time to cultivate. </p> - <blockquote> - <p>I've been building relationships, at least in Instagram and the WhatsApp cases, for years with the founders and the people that are involved in these companies, which made [it] so that when it became time or when we thought it was the right time to move, we felt like we had a good amount of context and had good relationships so that we could move quickly, which was competitively important and why a lot of these acquisitions, I think, came to us instead of our competitors and ended up being very good acquisitions over time that a lot of competitors wished they had gotten instead. </p> - </blockquote> - <p> He also stressed the need assure your target that you have a shared vision about how you will collaborate after the deal is put to bed. Zuckerberg said this was reason Facebook was able to acquire Oculus for less than its original $4 billion asking price.</p> - <blockquote>If this [deal] is going to happen, it's not going to be because we offer a lot of money, although we're going to have to offer a fair price for the company that is more than what they felt like they could do on their own. But they also need to feel like this was actually going to help their mission.</blockquote> - <p>When that doesn't work, Zuckerberg said scare tactics is an effective, if undesirable, way of persuading small startups that they face a better chance of survival if they have Facebook to guide their way rather than going it alone.</p> - <blockquote>That's less my thing, but I think if you are trying to help convince people that they want to join you, helping them understand all the pain that they would have to go through to build it out independently is a valuable tactic. </blockquote> - <p>It also pays to be weary of competing suitors for your startup, Zuckerberg said, and be willing to move fast to stave off rivals and get the deal done.</p> - <blockquote>Often, if a company knows we're offering something, they will offer more. So being able to move quickly not only increases our chance of being able to get a deal done if we want to, but it makes it so we don't have end up having to pay a lot more because the process drags out.</blockquote> - <p>It wasn't clear why these strategies didn't work on Snapchat CEO Evan Spiegel, who <a href="https://www.cnet.com/news/snapchat-said-to-rebuff-3-billion-offer-from-facebook/">famously rebuffed</a> a $3 billion takeover offer from Facebook in 2013.</p> - <p><em><strong>Tech Enabled:</strong> CNET chronicles tech's role in providing new kinds of accessibility. Check it out <a href="https://www.cnet.com/tech-enabled/">here</a>.</em><em><strong><br/></strong></em></p> - <p><em><strong>Technically Literate:</strong> Original works of short fiction with unique perspectives on tech, exclusively on CNET. <a href="https://www.cnet.com/technically-literate/">Here</a>.</em></p> - </div> -</div> +<div class="col-7 article-main-body row" data-component="lazyloadImages" itemprop="articleBody"> + + + + + <figure class="image image-medium
 pull-right" section="shortcodeImage"><span class="imageContainer"><span itemprop="image" itemscope="" itemtype="https://schema.org/ImageObject"><img alt="" class="" height="0" src="https://cnet1.cbsistatic.com/img/nAMdBzIE1ogVw5bOBZBaiJCt3Ro=/570x0/2014/03/21/863df5d9-e8b8-4b38-851b-5e3f77f2cf0e/mark-zuckerberg-facebook-home-10671610x407.jpg" width="570"></img><meta content="https://cnet1.cbsistatic.com/img/nAMdBzIE1ogVw5bOBZBaiJCt3Ro=/570x0/2014/03/21/863df5d9-e8b8-4b38-851b-5e3f77f2cf0e/mark-zuckerberg-facebook-home-10671610x407.jpg" itemprop="url"></meta><meta content="0" itemprop="height"></meta><meta content="570" itemprop="width"></meta></span></span> + <figcaption><span class="caption"><p style="">Facebook CEO Mark Zuckerberg, the man with the acquisition plan.</p></span><span class="credit">Photo by James Martin/CNET + </span></figcaption></figure><p style="">Anyone who has ever been involved in closing a billion-dollar acquisition deal will tell you that you don't go in without a clear, well thought out plan.</p> + + <p style="">Facebook CEO Mark Zuckerberg knows a thing or two about how to seal the deal on blockbuster buys. After all, he's the man behind his company's <a href="https://www.cnet.com/news/facebook-closes-19-billion-deal-for-whatsapp/" target="_blank">$19 billion acquisition</a> of WhatsApp, he <a href="https://www.cnet.com/news/zuckerberg-did-1-billion-instagram-deal-on-his-own/" target="_blank">personally brokered</a> its $1 billion buyout of <a href="https://www.cnet.com/news/why-facebook-plunked-down-1-billion-to-buy-instagram/" target="_blank">Instagram</a> and closed the <a href="https://www.cnet.com/news/facebook-to-buy-oculus-for-2-billion/" target="_blank">$3 billion deal</a> to buy Oculus VR.</p> + <p style="">Zuckerberg offered a primer on the strategies he and his company employ when they see an attractive target during testimony Tuesday <a href="https://www.cnet.com/news/zenimax-sues-oculus-over-virtual-reality-rift-tech/">in a lawsuit with ZeniMax Media</a>, which accuses Oculus and Facebook of "misappropriating" trade secrets and copyright infringement. At the heart of the lawsuit is technology that helped create liftoff for virtual reality, one of the <a data-component="externalLink" href="http://www.cbsnews.com/videos/the-reality-of-the-virtual-world/" target="_blank">hottest gadget trends today.</a></p> + <p style="">A key Facebook approach is building a long-term relationship with your target, Zuckerberg said at the trial. These deals don't just pop up over night, he said according to a transcript reviewed by <a data-component="externalLink" href="http://www.businessinsider.com/mark-zuckerberg-explains-facebooks-acquisition-strategy-2017-1" target="_blank">Business Insider</a>. They take time to cultivate. </p> + <blockquote> + <p style="">I've been building relationships, at least in Instagram and the WhatsApp cases, for years with the founders and the people that are involved in these companies, which made [it] so that when it became time or when we thought it was the right time to move, we felt like we had a good amount of context and had good relationships so that we could move quickly, which was competitively important and why a lot of these acquisitions, I think, came to us instead of our competitors and ended up being very good acquisitions over time that a lot of competitors wished they had gotten instead. </p> + </blockquote> + <p style=""> He also stressed the need assure your target that you have a shared vision about how you will collaborate after the deal is put to bed. Zuckerberg said this was reason Facebook was able to acquire Oculus for less than its original $4 billion asking price.</p> + <blockquote>If this [deal] is going to happen, it's not going to be because we offer a lot of money, although we're going to have to offer a fair price for the company that is more than what they felt like they could do on their own. But they also need to feel like this was actually going to help their mission.</blockquote> + + + + + + + <p style="">When that doesn't work, Zuckerberg said scare tactics is an effective, if undesirable, way of persuading small startups that they face a better chance of survival if they have Facebook to guide their way rather than going it alone.</p> + <blockquote>That's less my thing, but I think if you are trying to help convince people that they want to join you, helping them understand all the pain that they would have to go through to build it out independently is a valuable tactic. </blockquote> + <p style="">It also pays to be weary of competing suitors for your startup, Zuckerberg said, and be willing to move fast to stave off rivals and get the deal done.</p> + <blockquote>Often, if a company knows we're offering something, they will offer more. So being able to move quickly not only increases our chance of being able to get a deal done if we want to, but it makes it so we don't have end up having to pay a lot more because the process drags out.</blockquote> + <p style="">It wasn't clear why these strategies didn't work on Snapchat CEO Evan Spiegel, who <a href="https://www.cnet.com/news/snapchat-said-to-rebuff-3-billion-offer-from-facebook/">famously rebuffed</a> a $3 billion takeover offer from Facebook in 2013.</p> + + + + + + + <p style=""><em><strong>Tech Enabled:</strong> CNET chronicles tech's role in providing new kinds of accessibility. Check it out <a href="https://www.cnet.com/tech-enabled/">here</a>.</em><em><strong><br></br></strong></em></p> + <p style=""><em><strong>Technically Literate:</strong> Original works of short fiction with unique perspectives on tech, exclusively on CNET. <a href="https://www.cnet.com/technically-literate/">Here</a>.</em></p> + + + + + + + </div>
\ No newline at end of file diff --git a/test/test-pages/gmw/expected.html b/test/test-pages/gmw/expected.html index 58441ac..59d4a68 100644 --- a/test/test-pages/gmw/expected.html +++ b/test/test-pages/gmw/expected.html @@ -1,54 +1,57 @@ -<div id="readability-page-1" class="page"> - <div id="contentMain"> - <p> 翱翔于距地球数千公里的太空中，进入广袤漆黑的未知领域，是一项艰苦卓绝的工作。这让人感到巨大压力和极度恐慌。那么，为什么不能让宇航员来一杯“地球末日”鸡尾酒来放松一下？</p> - <p> 不幸的是，对于希望能喝上一杯的太空探险者，那些将他们送上太空的政府机构普遍禁止他们染指包括酒在内的含酒精饮料。</p> - <p> 但是，很快普通人都会有机会向人类“最终的边疆”出发——以平民化旅行的形式，去探索和殖民火星。确实，火星之旅将是一次令人感到痛苦的旅行，可能一去不复返并要几年时间才能完成，但是否应该允许参与者在旅程中痛饮一番？或至少携带能在火星上发酵自制酒精饮料的设备？</p> - <p align="center"><img id="45395168" alt="(Credit: Nasa)" src="http://imgtech.gmw.cn/attachement/jpg/site2/20170310/448a5bc1e2861a2c4e5929.jpg" title="宇航员在太空中喝酒会怎么样？后果很严重" /></p> - <p align="center"> - <span face="楷体"> 图注：巴兹?奥尔德林(Buzz Aldrin)可能是第二个在月球上行走的人，但他是第一个在月球上喝酒的人</span> - </p> - <p> 事实是，历史上酒与太空探险有一种复杂的关系。让我们来看看喝了酒的航天员究竟会发生什么—— 如果我们开始给予进入太空的人类更大的自由度，又可能会发生什么。</p> - <p> 人们普遍认为，当一个人所处的海拔越高，喝醉后会越容易感到头昏。因此，人们自然地想到，当人身处地球轨道上时，饮酒会对人体有更强烈的致眩作用。但这种说法可能不是正确的。</p> - <p> 事实上，有证据表明，早在上世纪八十年代就澄清了这一传言。1985年，美国联邦航空管理局（UFAA）开展了一项研究，以验证人在不同的海拔高度饮酒，是否会影响执行复杂任务时的表现和酒精测定仪的读数。</p> - <p> 在这项研究中，17名男子被要求在地面和一间模拟海拔3.7公里的房间内喝下一些伏特加。然后，他们被要求完成各种任务，包括心算口算问题、用操纵杆在示波器上跟踪灯光以及各种其它测试。研究人员发现，“酒精和海拔高度对酒精测定仪读数或完成任务的表现情况没有交互作用”。</p> - <p> 所以，人乘坐飞机时醉得更快是个传说？纽约州立大学（State University of New York，SUNY）社会学荣誉教授戴夫·汉森（Dave Hanson）研究酒精和饮酒超过40年，他认为确实如此。他说：“我不认为它（在太空中饮酒）会有任何不同。”</p> - <p> 他认为高原反应可能类似于宿醉，但它也可能类似于中毒。他说：“如果人们没有感受到充分的大气压力，他们也会觉得喝醉了一样。”</p> - <p> 相反，那些声称在飞机上比在地面上醉得更快的人，可能只是经历了“自认喝醉（think-drink）”效应，这种效应多年来已被广泛研究。它表明，如果人们认为自己喝醉了，那他们的一举一动会真的像喝醉了一样—— 而不是实际上他们真的醉了。</p> - <p> 汉森指出：“如果人们脑子里一直认为在飞机上酒精会对他们产生与平常不同的作用，那么他们乘坐飞机时真的会觉得酒精对他们产生了不同的作用。”</p> - <p> 所以，如果酒精对人体的物理效应与海拔高度无关，那么在国际空间站上睡前小饮一杯不应该是一个大问题，对吧？错了。</p> - <p> 美国宇航局约翰逊航天中心发言人丹尼尔·霍特(Daniel Huot)表示：“国际空间站上的宇航员不允许喝酒。在国际空间站上，酒精和其它挥发性化合物的使用受到控制，因为它们的挥发物可能对该站的水回收系统产生影响。”</p> - <p> 为此，国际空间站上的宇航员甚至没有被提供含有酒精的产品，例如漱口水、香水或须后水。如果在国际空间站上饮酒狂欢，溢出的啤酒也可能存在损坏设备的风险。</p> - <p align="center"><img id="45395150" alt="(Credit: iStock)" src="http://imgtech.gmw.cn/attachement/jpg/site2/20170310/448a5bc1e2861a2c4e592a.jpg" title="宇航员在太空中喝酒会怎么样？后果很严重" /></p> - <p class="pictext" align="center"> - <span face="楷体"> 图注：测试表明，有关人在高空中喝酒更容易醉的传言是不正确的</span> - </p> - <p> 然后是责任的问题。我们不允许汽车司机或飞机飞行员喝醉后驾驶，所以并不奇怪同样的规则适用于国际空间站上的宇航员。毕竟国际空间站的造价高达1500亿美元，而且在接近真空的太空中其运行速度达到了每小时27680公里。</p> - <p> 然而，2007年，美国宇航局(NASA)成立了一个负责调查宇航员健康状况的独立小组，称历史上该机构至少有两名宇航员在即将飞行前喝了大量的酒，但仍然被允许飞行。Nasa安全负责人随后的审查发现并没有证据支持这一指控。宇航员在飞行前12小时是严禁饮酒的，因为他们需要充分的思维能力和清醒的意识。</p> - <p> 出台这一规则的原因很清楚。在1985年UFAA开展的关于酒精在不同海拔高度影响的研究中，研究人员得出结论，酒精的影响与海拔高度无关。无论参与测试的人员在什么海拔高度喝酒，其酒精测量仪的读数都是一样的。他们的行为表现受到的影响也相同，但如果提供给测试人员的是安慰剂，则身处高空比身处海平面的行为表现要更差一些。这表明，无论是否摄入酒精，海拔高度可能对心理表现有轻微的影响。</p> - <p> 国际空间站禁止享用啤酒等有大量泡沫的饮料，可能有另一个原因：没有重力的帮助，液体和气体会在宇航员的胃里不停地翻滚，导致他们不断地打嗝。</p> - <p> 然而，尽管有严格的规则，这并不意味着太空中的人类不会接触发酵液体。在国际空间站上进行了大量有关酒精的实验—— 但没有发生让众人去饮酒的情况，所以没有人真正了解太空中人体对酒精具体有怎样的反应。</p> - <p> NASA发言人斯蒂芬妮?席尔霍尔茨(Stephanie Schierhol）表示：“我们研究了太空中宇航员身体的各种变化，包括微生物层面的。我们有一个营养计划，以确保他们的身体获得保持健康所需要的营养。显然，在实施‘天空实验室(skylab)’项目时，他们曾将雪利酒与宇航员一起送到太空中，但宇航员在零重力飞行时使用雪利酒的测试结果不太好。”天空实验室是美国第一座空间站。</p> - <p> 席尔霍尔茨补充说，在测试中使用雪利酒“引发呕吐反射，公众也反对”。</p> - <p> 也许最令人惊讶的是，人类在月球表面上喝的第一种液体是葡萄酒。前NASA宇航员巴兹·奥尔德林(Buzz Aldrin)在采访和他撰写的书中表示，1969年，在和尼尔·阿姆斯特朗(Neil Armstrong)走出登月舱之前的圣餐仪式上，他喝了少量葡萄酒。举行这一仪式时与地面的通信出现了暂停，因此这一过程从来没有播出。</p> - <p> 虽然Nasa对太空中酒精的使用有严格的规定，但在这方面俄罗斯过去似乎更为宽松。在其“和平号”空间站上，宇航员允许喝点干邑和伏特加。当他们发现国际空间站将严格禁止饮酒时，显然有不少怨言。</p> - <p> 然而，奇怪的是，酒仍然能通过各种方式出现在国际空间站上。2015年，日本酿酒商三得利(Suntory)的全球创新中心将该公司一些获奖的威士忌运送到国际空间站，参与一项旨在验证“能否通过利用微重力环境增强酒精饮料醇厚性”的实验。换句话说，在微重力下酒的陈酿过程可能不同，导致它的陈酿进程更快、味道更好。对此，地球上的每家酿酒商都想进一步地了解。</p> - <p> 几年前，即2011年9月至2014年9月，Nasa赞助了一个试验，研究微重力环境对威士忌中未发酵麦芽与烧焦橡木颗粒的影响，这两种物质能对威士忌的陈酿起帮助作用。在太空中逗留将近1000天后，用于测试的威士忌的单宁成分保持不变——但是太空中橡木颗粒产生了更高浓度的木质素分解产物，这种物质能赋予威士忌特别的风味。</p> - <p> Nasa表示：“这种试验不仅对麦芽威士忌行业有影响，而且对整个食品和饮料行业也有影响。送上太空的威士忌与对照样品之间的风味差异是如此显著，需要进一步分析以破解不同口味产生的原因。”</p> - <p> 因此，即使宇航员自己被禁止在地球轨道上饮酒，但他们正在做的工作可以提高在地上消费的酒的质量。</p> - <p> 相比之下，执行登陆火星任务的人将远离家乡几年，而不是几个月，因此可能会有人提出有关禁止饮酒的规定可以放松一些。</p> - <p> 然而，像戴夫?汉森这样的专家认为，继续禁止饮酒并没有什么害处。除了实际的安全问题，饮酒还可能有其它挑战。汉森认为，地球人存在许多社会文化方面的差异，而且人连续几年时间呆在一个狭小的空间里，很容易突然发怒，这些因素都使饮酒问题变得很棘手。</p> - <p align="center"><img id="45395153" alt="(Credit: David Frohman/Peachstate Historical Consulting Inc)" src="http://imgtech.gmw.cn/attachement/jpg/site2/20170310/448a5bc1e2861a2c4e592d.jpg" title="宇航员在太空中喝酒会怎么样？后果很严重" /> </p> - <p class="pictext" align="center"> - <span face="楷体"> 图注：奥尔德林的圣餐杯回到了地球上</span> - </p> - <p> 他说：“这是一个政治问题，也是一个文化方面的问题，但不是一个科学上的问题。这将是未来一个可能产生冲突领域，因为人们具有不同的文化背景，他们对饮酒的态度不同。”他进一步指出，如果你与穆斯林、摩门教徒或禁酒主义者分配在同一间宿舍怎么办？面对未来人们可能在一个没有期限的时间内呆在一个有限的空间里，需要“尽早解决”如何协调不同文化观点的问题。</p> - <p><ins></ins> 所以，当宇航员在地球轨道上时，将还不得不满足于通过欣赏外面的景色来振作精神，而不要指望沉溺于烈酒中。我们留在地球上的人，则可以准备好适量的香槟酒，以迎接他们的归来。</p> - <p> 原标题：他晚于阿姆斯特朗登月 却是首个敢在月球喝酒的人</p> - <p><strong> 出品︱网易科学人栏目组 胖胖</strong></p> - <p><strong> 作者︱春春</strong> - <a href="http://www.gmw.cn" target="_blank"><img src="https://img.gmw.cn/pic/content_logo.png" title="返回光明网首页" /></a> - </p> - - <p id="contentLiability">[责任编辑:肖春芳]</p> - </div> -</div> +<div id="contentMain"> + + + + <p> 翱翔于距地球数千公里的太空中，进入广袤漆黑的未知领域，是一项艰苦卓绝的工作。这让人感到巨大压力和极度恐慌。那么，为什么不能让宇航员来一杯“地球末日”鸡尾酒来放松一下？</p> + <p> 不幸的是，对于希望能喝上一杯的太空探险者，那些将他们送上太空的政府机构普遍禁止他们染指包括酒在内的含酒精饮料。</p> + <p> 但是，很快普通人都会有机会向人类“最终的边疆”出发——以平民化旅行的形式，去探索和殖民火星。确实，火星之旅将是一次令人感到痛苦的旅行，可能一去不复返并要几年时间才能完成，但是否应该允许参与者在旅程中痛饮一番？或至少携带能在火星上发酵自制酒精饮料的设备？</p> + <p align="center"><img alt="(Credit: Nasa)" id="45395168" src="http://imgtech.gmw.cn/attachement/jpg/site2/20170310/448a5bc1e2861a2c4e5929.jpg" title="宇航员在太空中喝酒会怎么样？后果很严重"></img></p> + <p align="center" style="TEXT-ALIGN: center"> + <span face="楷体" style="font-family: 楷体;"> 图注：巴兹?奥尔德林(Buzz Aldrin)可能是第二个在月球上行走的人，但他是第一个在月球上喝酒的人</span> + </p> + <p> 事实是，历史上酒与太空探险有一种复杂的关系。让我们来看看喝了酒的航天员究竟会发生什么—— 如果我们开始给予进入太空的人类更大的自由度，又可能会发生什么。</p> + <p> 人们普遍认为，当一个人所处的海拔越高，喝醉后会越容易感到头昏。因此，人们自然地想到，当人身处地球轨道上时，饮酒会对人体有更强烈的致眩作用。但这种说法可能不是正确的。</p> + <p> 事实上，有证据表明，早在上世纪八十年代就澄清了这一传言。1985年，美国联邦航空管理局（UFAA）开展了一项研究，以验证人在不同的海拔高度饮酒，是否会影响执行复杂任务时的表现和酒精测定仪的读数。</p> + <p> 在这项研究中，17名男子被要求在地面和一间模拟海拔3.7公里的房间内喝下一些伏特加。然后，他们被要求完成各种任务，包括心算口算问题、用操纵杆在示波器上跟踪灯光以及各种其它测试。研究人员发现，“酒精和海拔高度对酒精测定仪读数或完成任务的表现情况没有交互作用”。</p> + <p> 所以，人乘坐飞机时醉得更快是个传说？纽约州立大学（State University of New York，SUNY）社会学荣誉教授戴夫·汉森（Dave Hanson）研究酒精和饮酒超过40年，他认为确实如此。他说：“我不认为它（在太空中饮酒）会有任何不同。”</p> + <p> 他认为高原反应可能类似于宿醉，但它也可能类似于中毒。他说：“如果人们没有感受到充分的大气压力，他们也会觉得喝醉了一样。”</p> + <p> 相反，那些声称在飞机上比在地面上醉得更快的人，可能只是经历了“自认喝醉（think-drink）”效应，这种效应多年来已被广泛研究。它表明，如果人们认为自己喝醉了，那他们的一举一动会真的像喝醉了一样—— 而不是实际上他们真的醉了。</p> + <p> 汉森指出：“如果人们脑子里一直认为在飞机上酒精会对他们产生与平常不同的作用，那么他们乘坐飞机时真的会觉得酒精对他们产生了不同的作用。”</p> + <p> 所以，如果酒精对人体的物理效应与海拔高度无关，那么在国际空间站上睡前小饮一杯不应该是一个大问题，对吧？错了。</p> + <p> 美国宇航局约翰逊航天中心发言人丹尼尔·霍特(Daniel Huot)表示：“国际空间站上的宇航员不允许喝酒。在国际空间站上，酒精和其它挥发性化合物的使用受到控制，因为它们的挥发物可能对该站的水回收系统产生影响。”</p> + <p> 为此，国际空间站上的宇航员甚至没有被提供含有酒精的产品，例如漱口水、香水或须后水。如果在国际空间站上饮酒狂欢，溢出的啤酒也可能存在损坏设备的风险。</p> + <p align="center"><img alt="(Credit: iStock)" id="45395150" src="http://imgtech.gmw.cn/attachement/jpg/site2/20170310/448a5bc1e2861a2c4e592a.jpg" title="宇航员在太空中喝酒会怎么样？后果很严重"></img></p> + <p align="center" class="pictext"> + <span face="楷体" style="font-family: 楷体;"> 图注：测试表明，有关人在高空中喝酒更容易醉的传言是不正确的</span> + </p> + <p> 然后是责任的问题。我们不允许汽车司机或飞机飞行员喝醉后驾驶，所以并不奇怪同样的规则适用于国际空间站上的宇航员。毕竟国际空间站的造价高达1500亿美元，而且在接近真空的太空中其运行速度达到了每小时27680公里。</p> + <p> 然而，2007年，美国宇航局(NASA)成立了一个负责调查宇航员健康状况的独立小组，称历史上该机构至少有两名宇航员在即将飞行前喝了大量的酒，但仍然被允许飞行。Nasa安全负责人随后的审查发现并没有证据支持这一指控。宇航员在飞行前12小时是严禁饮酒的，因为他们需要充分的思维能力和清醒的意识。</p> + <p> 出台这一规则的原因很清楚。在1985年UFAA开展的关于酒精在不同海拔高度影响的研究中，研究人员得出结论，酒精的影响与海拔高度无关。无论参与测试的人员在什么海拔高度喝酒，其酒精测量仪的读数都是一样的。他们的行为表现受到的影响也相同，但如果提供给测试人员的是安慰剂，则身处高空比身处海平面的行为表现要更差一些。这表明，无论是否摄入酒精，海拔高度可能对心理表现有轻微的影响。</p> + <p> 国际空间站禁止享用啤酒等有大量泡沫的饮料，可能有另一个原因：没有重力的帮助，液体和气体会在宇航员的胃里不停地翻滚，导致他们不断地打嗝。</p> + <p> 然而，尽管有严格的规则，这并不意味着太空中的人类不会接触发酵液体。在国际空间站上进行了大量有关酒精的实验—— 但没有发生让众人去饮酒的情况，所以没有人真正了解太空中人体对酒精具体有怎样的反应。</p> + <p> NASA发言人斯蒂芬妮?席尔霍尔茨(Stephanie Schierhol）表示：“我们研究了太空中宇航员身体的各种变化，包括微生物层面的。我们有一个营养计划，以确保他们的身体获得保持健康所需要的营养。显然，在实施‘天空实验室(skylab)’项目时，他们曾将雪利酒与宇航员一起送到太空中，但宇航员在零重力飞行时使用雪利酒的测试结果不太好。”天空实验室是美国第一座空间站。</p> + <p> 席尔霍尔茨补充说，在测试中使用雪利酒“引发呕吐反射，公众也反对”。</p> + <p> 也许最令人惊讶的是，人类在月球表面上喝的第一种液体是葡萄酒。前NASA宇航员巴兹·奥尔德林(Buzz Aldrin)在采访和他撰写的书中表示，1969年，在和尼尔·阿姆斯特朗(Neil Armstrong)走出登月舱之前的圣餐仪式上，他喝了少量葡萄酒。举行这一仪式时与地面的通信出现了暂停，因此这一过程从来没有播出。</p> + <p> 虽然Nasa对太空中酒精的使用有严格的规定，但在这方面俄罗斯过去似乎更为宽松。在其“和平号”空间站上，宇航员允许喝点干邑和伏特加。当他们发现国际空间站将严格禁止饮酒时，显然有不少怨言。</p> + <p> 然而，奇怪的是，酒仍然能通过各种方式出现在国际空间站上。2015年，日本酿酒商三得利(Suntory)的全球创新中心将该公司一些获奖的威士忌运送到国际空间站，参与一项旨在验证“能否通过利用微重力环境增强酒精饮料醇厚性”的实验。换句话说，在微重力下酒的陈酿过程可能不同，导致它的陈酿进程更快、味道更好。对此，地球上的每家酿酒商都想进一步地了解。</p> + <p> 几年前，即2011年9月至2014年9月，Nasa赞助了一个试验，研究微重力环境对威士忌中未发酵麦芽与烧焦橡木颗粒的影响，这两种物质能对威士忌的陈酿起帮助作用。在太空中逗留将近1000天后，用于测试的威士忌的单宁成分保持不变——但是太空中橡木颗粒产生了更高浓度的木质素分解产物，这种物质能赋予威士忌特别的风味。</p> + <p> Nasa表示：“这种试验不仅对麦芽威士忌行业有影响，而且对整个食品和饮料行业也有影响。送上太空的威士忌与对照样品之间的风味差异是如此显著，需要进一步分析以破解不同口味产生的原因。”</p> + <p> 因此，即使宇航员自己被禁止在地球轨道上饮酒，但他们正在做的工作可以提高在地上消费的酒的质量。</p> + <p> 相比之下，执行登陆火星任务的人将远离家乡几年，而不是几个月，因此可能会有人提出有关禁止饮酒的规定可以放松一些。</p> + <p> 然而，像戴夫?汉森这样的专家认为，继续禁止饮酒并没有什么害处。除了实际的安全问题，饮酒还可能有其它挑战。汉森认为，地球人存在许多社会文化方面的差异，而且人连续几年时间呆在一个狭小的空间里，很容易突然发怒，这些因素都使饮酒问题变得很棘手。</p> + <p align="center"><img alt="(Credit: David Frohman/Peachstate Historical Consulting Inc)" id="45395153" src="http://imgtech.gmw.cn/attachement/jpg/site2/20170310/448a5bc1e2861a2c4e592d.jpg" title="宇航员在太空中喝酒会怎么样？后果很严重"></img></p> + <p align="center" class="pictext"> + <span face="楷体" style="font-family: 楷体;"> 图注：奥尔德林的圣餐杯回到了地球上</span> + </p> + <p> 他说：“这是一个政治问题，也是一个文化方面的问题，但不是一个科学上的问题。这将是未来一个可能产生冲突领域，因为人们具有不同的文化背景，他们对饮酒的态度不同。”他进一步指出，如果你与穆斯林、摩门教徒或禁酒主义者分配在同一间宿舍怎么办？面对未来人们可能在一个没有期限的时间内呆在一个有限的空间里，需要“尽早解决”如何协调不同文化观点的问题。</p> + <p><ins style="float:left;display:inline;margin:8px 13px 8px 0px;"></ins> 所以，当宇航员在地球轨道上时，将还不得不满足于通过欣赏外面的景色来振作精神，而不要指望沉溺于烈酒中。我们留在地球上的人，则可以准备好适量的香槟酒，以迎接他们的归来。</p> + <p> 原标题：他晚于阿姆斯特朗登月 却是首个敢在月球喝酒的人</p> + <p><strong> 出品︱网易科学人栏目组 胖胖</strong></p> + <p><strong> 作者︱春春</strong> + <a href="http://www.gmw.cn" target="_blank"><img src="https://img.gmw.cn/pic/content_logo.png" title="返回光明网首页"></img></a> + </p> + + <p>[责任编辑:肖春芳]</p> + + + </div>
\ No newline at end of file diff --git a/test/test-pages/msn/expected.html b/test/test-pages/msn/expected.html index e7c32a6..6442f6b 100644 --- a/test/test-pages/msn/expected.html +++ b/test/test-pages/msn/expected.html @@ -1,23 +1,18 @@ -<div id="readability-page-1" class="page"> - <article itemscope="" itemtype="http://schema.org/NewsArticle" class="articlecontent loaded" data-aop="article"> - <section class="articlebody" itemprop="articleBody" data-aop="articlebody"> - <p> - <span class="storyimage fullwidth inlineimage" data-aop="image"> -<span class="image" data-attrib="Provided by Business Insider Inc" data-caption="<span style="font-size:13px;">Nintendo/Apple</span>" data-id="55" data-m="{"i":55,"p":52,"n":"openModal","t":"articleImages","o":3}"> - <img alt="<span style="font-size:13px;">Nintendo/Apple</span>" data-src="{"default":{"load":"default","w":"73","h":"41","src":"//img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=410&w=728&m=6&q=60&o=f&l=f&x=1162&y=540"},"size3column":{"load":"default","w":"62","h":"35","src":"//img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=351&w=624&m=6&q=60&o=f&l=f&x=1162&y=540"},"size2column":{"load":"default","w":"62","h":"35","src":"//img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=351&w=624&m=6&q=60&o=f&l=f&x=1162&y=540"}}" src="http://img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=820&w=1456&m=6&q=60&o=f&l=f&x=1162&y=540" class="loaded" data-initial-set="true"/> -</span> - <span class="caption truncate"> +<article class="articlecontent loaded" data-aop="article" itemscope="" itemtype="http://schema.org/NewsArticle"><section class="articlebody" data-aop="articlebody" itemprop="articleBody"><p> + <span class="storyimage fullwidth inlineimage" data-aop="image"> +<span class="image" data-attrib="Provided by Business Insider Inc" data-caption="<span style="font-size:13px;">Nintendo/Apple</span>" data-id="55" data-m="{"i":55,"p":52,"n":"openModal","t":"articleImages","o":3}"> + <img alt="<span style="font-size:13px;">Nintendo/Apple</span>" class="loaded" data-initial-set="true" data-src="{"default":{"load":"default","w":"73","h":"41","src":"//img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=410&w=728&m=6&q=60&o=f&l=f&x=1162&y=540"},"size3column":{"load":"default","w":"62","h":"35","src":"//img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=351&w=624&m=6&q=60&o=f&l=f&x=1162&y=540"},"size2column":{"load":"default","w":"62","h":"35","src":"//img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=351&w=624&m=6&q=60&o=f&l=f&x=1162&y=540"}}" src="http://img-s-msn-com.akamaized.net/tenant/amp/entityid/AAkk5fh.img?h=820&w=1456&m=6&q=60&o=f&l=f&x=1162&y=540" style="width:73rem;height:41rem;"></img></span> + <span class="caption truncate"> <span class="attribution">© Provided by Business Insider Inc</span> - <span>Nintendo/Apple</span> - </span> - </span> - Nintendo and Apple shocked the world earlier this year by announcing "Super Mario Run," the legendary gaming company's first foray into mobile gaming. It's a Mario game you can play on your phone with just one hand, so what's not to love?</p> - <p>Thankfully, now we know when you can get it and for how much: "Super Mario Run" will launch on iPhone and iPad on December 15, for a flat fee of $9.99. You can play a sample of the game modes for free, but unlike most other mobile games that let you download for free but require money to keep playing, or access parts of the game, you can pay $10 to get everything right away. </p> - <p>In case you haven't heard, "Super Mario Run" is essentially a regular, side-scrolling "Super Mario" game with one key difference: You don't control Mario's movement. He runs automatically and all you do is tap the screen to jump.</p> - <p>The name and basic idea might sound like one of those endless score attack games like "Temple Run," but that's not the case. "Super Mario Run" is divided into hand-crafted levels with a clear end-point like any other Mario game, meaning you're essentially getting the Mario experience for $10 without needing to control his movement.</p> - <p>$10 might seem like a bit much compared to the $0 people pay for most mobile games, but it's possible the game has $10 worth of levels to play in it. It's also not iPhone exclusive, but the Android version will launch at a later, currently unknown date. </p> - <p>To see "Super Mario Run" in action, check out the footage below:</p> - <p class="video-container"><iframe allowfullscreen="" src="https://www.youtube.com/embed/E39ychZKnDI" frameborder="0" width="100%" height="450"></iframe></p> - </section> - </article> -</div> + <span style="font-size:13px;">Nintendo/Apple</span> + </span> + </span> + Nintendo and Apple shocked the world earlier this year by announcing "Super Mario Run," the legendary gaming company's first foray into mobile gaming. It's a Mario game you can play on your phone with just one hand, so what's not to love?</p> + <p>Thankfully, now we know when you can get it and for how much: "Super Mario Run" will launch on iPhone and iPad on December 15, for a flat fee of $9.99. You can play a sample of the game modes for free, but unlike most other mobile games that let you download for free but require money to keep playing, or access parts of the game, you can pay $10 to get everything right away. </p> + <p>In case you haven't heard, "Super Mario Run" is essentially a regular, side-scrolling "Super Mario" game with one key difference: You don't control Mario's movement. He runs automatically and all you do is tap the screen to jump.</p> + <p>The name and basic idea might sound like one of those endless score attack games like "Temple Run," but that's not the case. "Super Mario Run" is divided into hand-crafted levels with a clear end-point like any other Mario game, meaning you're essentially getting the Mario experience for $10 without needing to control his movement.</p> + <p>$10 might seem like a bit much compared to the $0 people pay for most mobile games, but it's possible the game has $10 worth of levels to play in it. It's also not iPhone exclusive, but the Android version will launch at a later, currently unknown date. </p> + <p>To see "Super Mario Run" in action, check out the footage below:</p> + <p><iframe allowfullscreen="" frameborder="0" height="450" src="https://www.youtube.com/embed/E39ychZKnDI" width="100%"></iframe></p> + + </section></article>
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