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| author | Andres Rey <[email protected]> | 2018-12-24 10:23:42 -0300 |
|---|---|---|
| committer | GitHub <[email protected]> | 2018-12-24 10:23:42 -0300 |
| commit | 09cb03f3f9ce9f8c4193f4240f68d460fe085a63 (patch) | |
| tree | 1bbf7641fcb93cee80ba873bce90a4bc9e3229f5 /test/test-pages/blogger/expected-metadata.json | |
| parent | 4327b730cb9a827a71dfa35a8eaf9062a1a481e7 (diff) | |
| parent | baf3a68f1736238e8270ceec83822ee3a1f923a3 (diff) | |
Merge pull request #75 from maludecks/sitename-feature
Add getSiteName feature
Diffstat (limited to 'test/test-pages/blogger/expected-metadata.json')
| -rw-r--r-- | test/test-pages/blogger/expected-metadata.json | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/test/test-pages/blogger/expected-metadata.json b/test/test-pages/blogger/expected-metadata.json index 43a34d6..a081c88 100644 --- a/test/test-pages/blogger/expected-metadata.json +++ b/test/test-pages/blogger/expected-metadata.json @@ -3,5 +3,6 @@ "Direction": null, "Excerpt": "I've written a couple of posts in the past few months but they were all for the blog at work so I figured I'm long overdue for one on Silic...", "Image": "https:\/\/1.bp.blogspot.com\/-YIPC5jkXkDE\/Vy7YPSqFKWI\/AAAAAAAAAxI\/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB\/w1200-h630-p-nu\/block-diagram.png", - "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices" -}
\ No newline at end of file + "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices", + "SiteName": null +} |