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authorMaria Luiza Soares <[email protected]>2018-12-21 14:47:40 +0100
committerMalu Decks <[email protected]>2018-12-23 05:37:44 +0100
commitb63c65bdf86c241ae4e1dbe8978bcc341a1742fd (patch)
treeb7d5f3b3d797e79af678b4d722fd80e4fdcddebf /test/test-pages/blogger
parent01f5f7c94e4c99643ed41ba26db6efcc018d4b07 (diff)
Update all tests to assert on getSiteName outcome
Diffstat (limited to 'test/test-pages/blogger')
-rw-r--r--test/test-pages/blogger/expected-metadata.json5
1 files changed, 3 insertions, 2 deletions
diff --git a/test/test-pages/blogger/expected-metadata.json b/test/test-pages/blogger/expected-metadata.json
index 43a34d6..a081c88 100644
--- a/test/test-pages/blogger/expected-metadata.json
+++ b/test/test-pages/blogger/expected-metadata.json
@@ -3,5 +3,6 @@
"Direction": null,
"Excerpt": "I've written a couple of posts in the past few months but they were all for the blog at work so I figured I'm long overdue for one on Silic...",
"Image": "https:\/\/1.bp.blogspot.com\/-YIPC5jkXkDE\/Vy7YPSqFKWI\/AAAAAAAAAxI\/a7D6Ji2GxoUvcrwUkI4RLZcr2LFQEJCTACLcB\/w1200-h630-p-nu\/block-diagram.png",
- "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices"
-} \ No newline at end of file
+ "Title": "Open Verilog flow for Silego GreenPak4 programmable logic devices",
+ "SiteName": null
+}